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SDRAM (Rev. 0.3)
MITSUBISHI LSIs
Feb `97 Preliminary
M5M4V4S40CTP-12, -15
4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM
PRELIMINARY
Some of contents are described for general products and are subject to change without notice.
DESCRIPTION
The M5M4V4S40CTP is a 2-bank x 131,072-word x 16-bit Synchronous DRAM, with LVTTL interface. All inputs and outputs are referenced to the rising edge of CLK. The M5M4V4S40CTP achieves very high speed data rates up to 83MHz, and is suitable for main memory or graphic memory in computer systems.
Vdd DQ0 DQ1 VssQ DQ2 DQ3 VddQ DQ4 DQ5 VssQ DQ6 DQ7 VddQ DQML /WE /CAS /RAS /CS BA A8 A0 A1 A2 A3 Vdd
PIN CONFIGURATION (TOP VIEW)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 Vss DQ15 DQ14 VssQ DQ13 DQ12 VddQ DQ11 DQ10 VssQ DQ9 DQ8 VddQ NC DQMU CLK CKE NC NC NC A7 A6 A5 A4 Vss
FEATURES
- Single 3.3v0.3v power supply - Clock frequency 83MHz / 67MHz - Fully synchronous operation referenced to clock rising edge - Dual bank operation controlled by BA(Bank Address) - /CAS latency- 1/2/3 (programmable) - Burst length- 1/2/4/8/FP (programmable) - Sequential and interleave burst (programmable) - Byte control by DQMU and DQML - Random column access - Auto precharge / All bank precharge controlled by A8 - Auto and self refresh - 1024 refresh cycles /16.4ms CLK - LVTTL Interface CKE - 400-mil, 50-pin Thin Small Outline Package /CS (TSOP II) with 0.8mm lead pitch /RAS
Max. Frequency M5M4V4S40CTP-12 M5M4V4S40CTP-15 83MHz 67MHz
CLK Access Time 8ns 9ns
/CAS /WE DQ0-15 DQMU DQML A0-8 BA Vdd VddQ Vss VssQ
: Master Clock : Clock Enable : Chip Select : Row Address Strobe : Column Address Strobe : Write Enable : Data I/O : Upper Output Disable/ Write Mask : Lower Output Disable/ Write Mask : Address Input : Bank Address : Power Supply : Power Supply for Output : Ground : Ground for Output
400mil 50pin TSOP(II)
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SDRAM (Rev. 0.3)
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Feb `97 Preliminary
M5M4V4S40CTP-12, -15
4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM
BLOCK DIAGRAM
DQ0-15
I/O Buffer
Memory Array Bank #0
Memory Array Bank #1
Mode Register Control Circuitry
Address Buffer Clock Buffer
Control Signal Buffer
A0-8
BA
/CS /RAS /CAS /WE
DQML DQMU
CLK
CKE
Type Designation Code
These rules are only applied to the Synchronous DRAM family.
M 5M 4 V 4 S 4 0 C TP - 12
Cycle Time (min.) 12: 12ns, 15: 15ns Package Type TP: TSOP(II) Process Generation Function 0: Random Column, 1: 2N-rule Organization 2 n 4: x16 Synchronous DRAM Density 4:4M bits Interface V:LVTTL Memory Style (DRAM) Use, Recommended Operating Conditions, etc Mitsubishi Main Designation
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Feb `97 Preliminary
M5M4V4S40CTP-12, -15
4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM
PIN FUNCTION
CLK Input Master Clock: All other inputs are referenced to the rising edge of CLK. Clock Enable: CKE controls the internal clock. When CKE is low, the internal clock for the following cycle is disabled. CKE is also used to select auto and self refresh. After self-refresh mode is started, CKE acts as an asynchronous input to maintain and exit the mode. Chip Select: When /CS is high, all commands are inhibited. /RAS, /CAS, and /WE are used to define basic commands. A0-8 specify the Row and Column addresses within the selected bank. The Row Address is set by A0-8 and the Column Address is set by A0-7. A8 is also used to indicate the precharge option. When A8 is high during read or write command, an auto precharge is performed. When A8 is high during a precharge command, both banks are precharged. Bank Address: BA is not simply A9. BA specifies the bank to which a command is applied. BA must be set during the ACT, PRE, READ, and WRITE commands. Data In and data out are referenced to the rising edge of CLK. Lower Din(0-7) Mask; Lower Dout(0-7) Disable; When DQML is high during burst write Din(0-7) for the current cycle is masked. When DQML is high during burst read Dout(0-7) is disabled two cycles later. Upper Din(8-15) Mask; Upper Dout(8-15) Disable; When DQMU is high during burst write Din(8-15) for the current cycle is masked. When DQMU is high during burst read Dout(8-15) is disabled two cycles later. Power Supply for the memory array and peripheral circuitry. Power Supply for the output buffers only.
CKE
Input
/CS /RAS, /CAS, /WE
Input Input
A0-8
Input
BA
Input
DQ0-15
Input / Output
DQML
Input
DQMU
Input
Vdd, Vss VddQ, VssQ
Power Supply Power Supply
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Feb `97 Preliminary
M5M4V4S40CTP-12, -15
4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM
BASIC FUNCTIONS
The M5M4V4S40CTP has the following basic functions, bank (row) activate, burst read/write, bank (row) precharge, and auto/self refresh. Each command is defined by the control signals (/RAS, /CAS and /WE) at the rising edge of CLK. The inputs /CS ,CKE and A8 are used for chip select, refresh options, and precharge options, respectively. Please see the command truth table for detailed definitions.
CLK /CS /RAS /CAS /WE CKE A8
Chip Select : L=select, H=deselect Command Command Command Refresh Option @refresh command Precharge Option @precharge or read/write command define basic commands
Activate (ACT) [/RAS =L, /CAS =/WE =H] The ACT command activates a row in an idle bank. The bank address, BA, is used to select which of the two banks will be activated. Read (READ) [/RAS =H, /CAS =L, /WE =H] The READ command starts burst read from the active bank indicated by BA. The first output data appears after /CAS latency. If A8 =H when READ is issued the bank is automatically precharged after the last burst read (READA). Note: READA is not valid for FP burst operations. Write (WRITE) [/RAS =H, /CAS =/WE =L] The WRITE command starts burst write to the active bank indicated by BA. Total data length to be written is set by burst length. If A8 =H when WRITE is issued the bank is automatically precharged after the last burst write (WRITEA). Note: WRITEA is not valid for FP burst operations. Precharge (PRE) [/RAS =L, /CAS =H, /WE =L] The PRE command deactivates the active bank indicated by BA. This command also terminates burst read and write operations. If A8 =H when PRE is issued both banks are automatically precharged (PREA). Auto-Refresh (REFA) [/RAS =/CAS =L, /WE =CKE =H] The REFA command starts an auto-refresh cycle. The refresh address, including the bank address, is generated internally. After this command, the banks are precharged automatically.
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4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM
COMMAND TRUTH TABLE
COMMAND Deselect No Operation Row Address Entry & Bank Activate Single Bank Precharge Precharge All Banks Column Address Entry & Write Column Address Entry & Write with AutoPrecharge Column Address Entry & Read Column Address Entry & Read with AutoPrecharge Auto-Refresh Self-Refresh Entry Self-Refresh Exit Burst Terminate Mode Register Set MNEMONIC DESEL NOP ACT PRE PREA WRITE CKE n-1 H H H H H H CKE n X X X X X X /CS H L L L L L /RAS X H L L L H /CAS X H H H H L /WE X H H L L L BA X X V V X V A8 X X V L H L A0-7 X X V X X V
WRITEA
H
X
L
H
L
L
V
H
V
READ
H
X
L
H
L
H
V
L
V
READA REFA REFS REFSX TBST MRS
H H H L L H H
X H L H H X X
L L L H L L L
H L L X H H L
L L L X H H L
H H H X H L L
V X X X X X V
H X X X X X L
V X X X X X V*1
H=High Level, L=Low Level, V=Valid, X=Don't Care, n=CLK cycle number NOTE: 1. A7 =0, A0-A6 =Mode Address
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M5M4V4S40CTP-12, -15
4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM
FUNCTION TRUTH TABLE
Current State IDLE /CS H L L L L L L L ROW ACTIVE H L L L L L L L L READ H L L L /RAS X H H H L L L L X H H H H L L L L X H H H /CAS X H H L H H L L X H H L L H H L L X H H L /WE X H L X H L H L X H L H L H L H L X H L H X X X BA, CA, A8 BA, RA BA, A8 X Op-Code, Mode-Add X X X BA, CA, A8 BA, CA, A8 BA, RA BA, A8 X Op-Code, Mode-Add X X X BA, CA, A8 Address Command DESEL NOP TBST NOP NOP ILLEGAL*2 Action
READ / WRITE ILLEGAL*2 ACT PRE / PREA REFA MRS DESEL NOP TBST Bank Active, Latch RA NOP*4 Auto-Refresh*5 Mode Register Set*5 NOP NOP NOP
Begin Read, Latch CA, READ / READA Determine Auto-Precharge WRITE / WRITEA ACT PRE / PREA REFA MRS DESEL NOP TBST Begin Write, Latch CA, Determine Auto-Precharge Bank Active / ILLEGAL*2 Precharge / Precharge All ILLEGAL ILLEGAL NOP (Continue Burst to END) NOP (Continue Burst to END) Terminate Burst
Terminate Burst, Latch CA, READ / READA Begin New Read, Determine Auto-Precharge*3 WRITE / WRITEA ACT PRE / PREA REFA MRS Terminate Burst, Latch CA, Begin Write, Determine AutoPrecharge*3 Bank Active / ILLEGAL*2 Terminate Burst, Precharge ILLEGAL ILLEGAL
L L L L L
H L L L L
L H H L L
L H L H L
BA, CA, A8 BA, RA BA, A8 X Op-Code, Mode-Add
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FUNCTION TRUTH TABLE
Current State WRITE /CS H L L L /RAS X H H H /CAS X H H L
M5M4V4S40CTP-12, -15
(continued)
/WE X H L H X X X BA, CA, A8 Address Command DESEL NOP TBST Action NOP (Continue Burst to END) NOP (Continue Burst to END) Terminate Burst
4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM
Terminate Burst, Latch CA, READ / READA Begin Read, Determine AutoPrecharge*3 WRITE / WRITEA ACT PRE / PREA REFA MRS DESEL NOP TBST Terminate Burst, Latch CA, Begin Write, Determine AutoPrecharge*3 Bank Active / ILLEGAL*2 Terminate Burst, Precharge ILLEGAL ILLEGAL NOP (Continue Burst to END) NOP (Continue Burst to END) ILLEGAL
L L L L L READ with AUTO PRECHARGE H L L L L L L L L WRITE with AUTO PRECHARGE H L L L L L L L L
H L L L L X H H H H L L L L X H H H H L L L L
L H H L L X H H L L H H L L X H H L L H H L L
L H L H L X H L H L H L H L X H L H L H L H L
BA, CA, A8 BA, RA BA, A8 X Op-Code, Mode-Add X X X BA, CA, A8 BA, CA, A8 BA, RA BA, A8 X Op-Code, Mode-Add X X X BA, CA, A8 BA, CA, A8 BA, RA BA, A8 X Op-Code, Mode-Add
READ / READA ILLEGAL WRITE / WRITEA ACT PRE / PREA REFA MRS DESEL NOP TBST ILLEGAL Bank Active / ILLEGAL*2 ILLEGAL*2 ILLEGAL ILLEGAL NOP (Continue Burst to END) NOP (Continue Burst to END) ILLEGAL
READ / READA ILLEGAL WRITE / WRITEA ACT PRE / PREA REFA MRS ILLEGAL Bank Active / ILLEGAL*2 ILLEGAL*2 ILLEGAL ILLEGAL
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M5M4V4S40CTP-12, -15
4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM
FUNCTION TRUTH TABLE (continued)
Current State PRE CHARGING /CS H L L L L L L L ROW ACTIVATING H L L L L L L L WRITE RECOVERING H L L L L L L L /RAS X H H H L L L L X H H H L L L L X H H H L L L L /CAS X H H L H H L L X H H L H H L L X H H L H H L L /WE X H L X H L H L X H L X H L H L X H L X H L H L X X X BA, CA, A8 BA, RA BA, A8 X Op-Code, Mode-Add X X X BA, CA, A8 BA, RA BA, A8 X Op-Code, Mode-Add X X X BA, CA, A8 BA, RA BA, A8 X Op-Code, Mode-Add Address Command DESEL NOP TBST Action NOP (Idle after tRP) NOP (Idle after tRP) ILLEGAL*2
READ / WRITE ILLEGAL*2 ACT PRE / PREA REFA MRS DESEL NOP TBST ILLEGAL*2 NOP*4 (Idle after tRP) ILLEGAL ILLEGAL NOP (Row Active after tRCD) NOP (Row Active after tRCD) ILLEGAL*2
READ / WRITE ILLEGAL*2 ACT PRE / PREA REFA MRS DESEL NOP TBST ILLEGAL*2 ILLEGAL*2 ILLEGAL ILLEGAL NOP NOP ILLEGAL*2
READ / WRITE ILLEGAL*2 ACT PRE / PREA REFA MRS ILLEGAL*2 ILLEGAL*2 ILLEGAL ILLEGAL
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M5M4V4S40CTP-12, -15
4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM
FUNCTION TRUTH TABLE (continued)
Current State REFRESHING /CS H L L L L L L L MODE REGISTER SETTING H L L L L L L L /RAS X H H H L L L L X H H H L L L L /CAS X H H L H H L L X H H L H H L L /WE X H L X H L H L X H L X H L H L X X X BA, CA, A8 BA, RA BA, A8 X Op-Code, Mode-Add X X X BA, CA, A8 BA, RA BA, A8 X Op-Code, Mode-Add Address Command DESEL NOP TBST Action NOP (Idle after tRC) NOP (Idle after tRC) ILLEGAL
READ / WRITE ILLEGAL ACT PRE / PREA REFA MRS DESEL NOP TBST ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP (Idle after tRSC) NOP (Idle after tRSC) ILLEGAL
READ / WRITE ILLEGAL ACT PRE / PREA REFA MRS ILLEGAL ILLEGAL ILLEGAL ILLEGAL
ABBREVIATIONS: H=High Level, L=Low Level, X=Don't Care BA=Bank Address, RA=Row Address, CA=Column Address, NOP=No Operation NOTES: 1. All entries assume that CKE was High during the preceding clock cycle and the current clock cycle. 2. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA, depending on the state of that bank. 3. Must satisfy bus contention, bus turn around, write recovery requirements. 4. NOP to bank precharging or in idle state. May precharge bank indicated by BA. 5. ILLEGAL if any bank is not idle. ILLEGAL = Device operation and/or data-integrity are not guaranteed.
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4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM
FUNCTION TRUTH TABLE for CKE
Current State SELFREFRESH*1 CKE n-1 H L L L L L L POWER DOWN H L L ALL BANKS IDLE*2 H H H H H H H L ANY STATE other than listed above H H L L CKE n X H H H H H L X H L H L L L L L L X H L H L /CS X H L L L L X X X X X L H L L L L X X X X X /RAS /CAS X X H H H L X X X X X L X H H H L X X X X X X X H H L X X X X X X L X H H L X X X X X X /WE X X H L X X X X X X X H X H L X X X X X X X Add X X X X X X X X X X X X X X X X X X X X X X INVALID Exit Self-Refresh (Idle after tRC) Exit Self-Refresh (Idle after tRC) ILLEGAL ILLEGAL ILLEGAL NOP (Maintain Self-Refresh) INVALID Exit Power Down to Idle NOP (Maintain Self-Refresh) Refer to Function Truth Table Enter Self-Refresh Enter Power Down Enter Power Down ILLEGAL ILLEGAL ILLEGAL Refer to Current State =Power Down Refer to Function Truth Table Begin CLK Suspend at Next Cycle*3 Exit CLK Suspend at Next Cycle*3 Maintain CLK Suspend Action
ABBREVIATIONS: H=High Level, L=Low Level, X=Don't Care NOTES: 1. CKE Low to High transition will re-enable CLK and other inputs asynchronously . A minimum setup time must be satisfied before any command other than EXIT. 2. Power-Down and Self-Refresh can be entered only from the All Banks Idle State. 3. Must be legal command.
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4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM
SIMPLIFIED STATE DIAGRAM
SELF REFRESH
REFS REFSX MRS
MODE REGISTER SET
REFA
IDLE
AUTO REFRESH
CKEL
CLK SUSPEND
CKEH ACT CKEL
POWER DOWN
CKEH TBST(for Full Page) TBST(for Full Page)
ROW ACTIVE
WRITE
READ READA CKEL READ WRITE
WRITEA CKEL
WRITE SUSPEND
WRITE
CKEH
READ
CKEH
READ SUSPEND
WRITEA WRITEA CKEL READA
READA
CKEL
WRITEA SUSPEND
WRITEA
CKEH PRE
PRE PRE
READA
CKEH
READA SUSPEND
POWER APPLIED
POWER ON
PRE
PRE CHARGE Automatic Sequence Command Sequence
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4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM
POWER ON SEQUENCE
Before starting normal operations, the following power on sequence is necessary to prevent the SDRAM from damage and malfunctions. 1. Apply power and start the clock, CLK. Attempt to maintain CKE high, DQMU/DQML high and NOP conditions on the inputs. 2. Maintain stable power, stable clock, and NOP input conditions for a minimum of 500s. 3. Issue precharge commands for all banks (PRE or PREA). 4. After all banks reach an idle state and after the row the precharge time (tRP) issue 8 or more auto-refresh commands. 5. Finally, issue a mode register set (MRS) command to initialize the mode register. After tRSC from the MRS command, the SDRAM will be in an idle state and ready for normal operations.
MODE REGISTER
Burst Length, Burst Type, and /CAS Latency can be programmed by setting the mode register (MRS). The mode register stores this data until the next MRS command. An MRS command can only be issued when both banks are idle. After tRSC from an MRS operation, the SDRAM is ready for new commands.
CLK /CS /RAS BA A8 A7 0 A6 A5 A4 A3 BT A2 A1 BL A0 /CAS /WE BA, A8 -A0
V
OPCODE
LTMODE
CL 000 001 010 011 1XX
/CAS LATENCY R 1 2 3 R
BL 000 001 010 011 100 101 110 111
BT= 0 BT= 1 1 2 4 8 R R R F.P. 1 2 4 8 R R R R
LATENCY MODE OP 00 01 10 11
BURST LENGTH
OPCODE
Burst read / Burst write R Burst read / Single write R
BURST TYPE
0 1
SEQUENTIAL INTERLEAVED R is Reserved for Future Use F.P. = Full Page (256)
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4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM [ CAS LATENCY ] /CAS latency, CL, is used to synchronize the first output data with the CLK frequency, i.e., the speed of CLK determines which CL should be used. The DRAM column access, tCAC, determines the CL timing requirements. /CAS Latency Timing (BL=4)
CLK Command
ACT tRCD READ
Address DQ DQ DQ
X
Y Q0 Q1 Q0 Q2 Q1 Q0 Q3 Q2 Q1 Q3 Q2 Q3
CL=1 CL=2 CL=3
[ BURST LENGTH ] The burst length, BL, determines the number of consecutive writes or reads that will be automatically performed after the initial write or read command. For BL=1,2,4,8 the output data is tristated (Hi-Z) after the last read. For BL=FP (Full Page) the TBST (Burst Terminate) command must be used to stop the output of data.
tRCD
Burst Length Timing (CL=2)
CLK
Command
ACT
READ
Address DQ DQ DQ DQ DQ
X
Y Q0 Q0 Q0 Q0 Q0 Q1 Q1 Q1 Q1 Q2 Q2 Q2 Q3 Q3 Q3 Q4 Q4 Q5 Q5 Q6 Q6 Q7 Q7 Q8 Q255 Q0 Q1
BL=1 BL=2 BL=4 BL=8 BL=FP
Full Page counter rolls over and continues to count.
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4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM [ BURST ADDRESS SEQUENCE ]
CLK Command Address DQ CL= 3 BL= 4 /CAS Latency
Read Y Q0 Q1 Q2 Q3 Write Y D0 D1 D2 D3
Burst Length
Burst Length
Internal addresses are determined by Burst Type. Initial Address BL A2 0 0 0 0 1 1 1 1 A1 A0 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 8 0 1 0 1 0 1 4 0 1 0 2 1 1 0 1 0 2 3 0 3 0 1 0 1 1 2 2 3 0 3 2 1 0 1 1 0 4 5 6 7 0 1 5 6 7 0 1 2 6 7 0 1 2 3 7 0 1 2 3 0 0 1 2 3 1 2 3 4 2 3 4 5 3 4 5 6 4 5 6 7 0 1 5 4 7 6 1 0 6 7 4 5 2 3 7 6 5 4 3 2 0 1 2 3 1 0 3 2 2 3 0 1 3 2 1 0 0 1 2 3 1 2 3 4 2 3 4 5 Column Addressing / Burst Type Sequential 3 4 5 6 4 5 6 7 5 6 7 0 6 7 0 1 7 0 1 2 0 1 2 3 1 0 3 2 2 3 0 1 Interleaved 3 2 1 0 4 5 6 7 5 4 7 6 6 7 4 5 7 6 5 4
Note: For FP Burst the Burst Type must be set to sequential.
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4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM
OPERATIONAL DESCRIPTION
BANK ACTIVATE The SDRAM has two independent banks. Each bank is activated by the ACT command with the bank address (BA). A row inside the bank is selected by the row address A8-0. The minimum activation interval between one bank and the opposite bank is tRRD.
PRECHARGE The PRE command deactivates the bank indicated by BA. When both banks are active, the precharge all command (PREA, PRE + A8=H) can be used to deactivate them at the same time. After tRP from the precharge, an ACT command can be issued. Bank Activation and Precharge All (BL=4, CL=3)
CLK Command A0-7 A8 BA DQ
ACT tRRD Xa tRCD Xa 0 Xb 1 0 0 Qa0 Qa1 Qa2 Qa3 1 Xb 1 Xb Y ACT READ tRAS PRE tRP Xb ACT
Precharge all
READ A READ command can be issued after tRCD from bank activation (ACT). Output data is available after the /CAS Latency from the READ, followed by (BL -1) consecutive output data (Burst Length = BL). The start address is specified by A7-0, and the address sequence of the burst data is defined by the Burst Type. A READ command may be applied to any active bank. This allows the row precharge time (tRP) to be hidden behind continuous output data (in case of BL=4) by interleaving the dual banks. When A8 is high at a READ command, the auto-precharge (READA) is performed. During READA the READ, WRITE, PRE, and ACT commands to the same bank are inhibited until the internal precharge is complete. Internal precharge start timing depends on /CAS Latency. The next ACT command can be issued after tRP from the precharge (PRE).
Note: READA is not allowed for FP burst length operations. The SDRAM must be manually precharged.
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Dual Bank Interleaving READ (BL=4, CL=3)
4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM
CLK Command A0-7 A8 BA DQ
/CAS latency ACT tRCD Xa Xa 0 Y 0 0 Xb Xb 1 Qa0 Y 0 1 Qa1 0 0 Qa2 Qa3 Qb0 Qb1 Qb2 READ ACT READ PRE
Burst Length
READ with Auto-Precharge (BL=4, CL=3)
CLK Command A0-7 A8 BA DQ
ACT tRCD Xa Xa 0 Y 1 0 Qa0 Qa1 Qa2 Qa3 READ tRP Xa Xa 0 ACT
Internal Precharge Begins
READ Auto-Precharge Timing (BL=4)
CLK Command CL=3 CL=2 CL=1 DQ DQ DQ
Qa0 Qa0 Qa1 ACT READ Qa0 Qa1 Qa2 Qa1 Qa2 Qa3 Qa2 Qa3 Qa3
Internal Precharge Begins
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4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM WRITE A WRITE command can be issued after tRCD from the bank activation (ACT). Input data is written to the SDRAM beginning on the rising edge of CLK in the same cycle that the WRITE command is applied. The remaining input data will be clocked in on the subsequent CLK cycles. The number of writes depends on the BL set in the mode register. The start address is specified by A7-0 and the address sequence is defined by the Burst Type. A WRITE command may be applied to any active bank. This allows the row precharge time (tRP) to be hidden behind continuous input data. Write recovery time (tWR) is required between the last write and subsequent precharge (PRE) inside of a bank. When A8 is high during a WRITE command (WRITEA) , an auto precharge is performed after the last data is input. All commands (READ, WRITE, PRE, ACT) to the same bank are inhibited until the internal precharge is complete. The internal precharge begins at tWR after the last input data cycle. The next ACT command can be issued after tRP. WRITEA cannot be used for FP burst length operations. The Mode Register can be programmed for burst read and single write. In this mode the write data is only clocked in when the WRITE command is issued and the remaining burst length is ignored. The read data burst length is unaffected while in this mode. Dual Bank Interleaving WRITE (BL=4)
CLK Command A0-7 A8 BA DQ
ACT tRCD Xa Xa 0 Y 0 0 Da0 Xb Xb 1 Da1 Da2 Da3 Write ACT tRCD Y tWR 0 1 Db0 0 0 Db1 Db2 Db3 Write PRE
Burst Length
WRITE with Auto-Precharge (BL=4)
CLK Command A0-7 A8 BA DQ
ACT tRCD Xa Xa 0 Y 1 0 tWR Da0 Da1 Da2 Da3 Write tRP Xa Xa 0 ACT
Internal precharge begins
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SDRAM (Rev. 0.3)
MITSUBISHI LSIs
Feb `97 Preliminary
M5M4V4S40CTP-12, -15
4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM BURST INTERRUPTION [ Read Interrupted by Read ] A burst read operation can be interrupted by a new read of the same or opposite bank. M5M4V4S40CTP allows random column accesses. READ to READ interval is a minimum of one CLK. Read Interrupted by Read (BL=4, CL=3)
CLK Command A0-7 A8 BA DQ
READ READ Yi 0 0 Yj 0 0 READ Yk 0 1 Qai0 Qaj0 READ Yl 0 0 Qaj1 Qbk0 Qbk1 Qbk2 Qal0 Qal1 Qal2 Qal3
[ Read Interrupted by Write ] A burst read operation can be interrupted by a write to the same or opposite bank. For this operation, the DQ's should be controlled by using DQMU and DQML to prevent bus contention. The output is disabled two cycles automatically after WRITE assertion. Random column access is allowed. Read Interrupted by Write (BL=4, CL=3)
CLK Command A0-7 A8 BA DQMU DQML Q D
Qai0 Daj0 Daj1 Daj2 Daj3 Read Yi 0 0 Write Yj 0 0
DQMU/DQML control
Write control
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SDRAM (Rev. 0.3)
MITSUBISHI LSIs
Feb `97 Preliminary
M5M4V4S40CTP-12, -15
4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM [ Read Interrupted by Precharge ] A burst read operation can be interrupted by a precharge of the same bank. The READ to PRE interval is a minimum of one CLK. A PRE command disables the data output, depending on the /CAS latency. The figures below show examples of how the output data is terminated with a PRE command.
Read Interrupted by Precharge (BL=4)
CLK
Command
READ
PRE
DQ
Q0
Q1
Q2
Q3
Command
READ
PRE
CL=3
DQ Q0 Q1 Q2
Command
READ
PRE
DQ
Q0
Command
READ
PRE
DQ
Q0
Q1
Q2
Q3
Command
READ
PRE
CL=2
DQ Q0 Q1 Q2
Command
READ
PRE
DQ
Q0
Command
READ
PRE
DQ
Q0
Q1
Q2
Q3
CL=1
Command READ PRE
DQ
Q0
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SDRAM (Rev. 0.3)
MITSUBISHI LSIs
Feb `97 Preliminary
M5M4V4S40CTP-12, -15
4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM [ Read Interrupted by Burst Terminate ] Similar to a precharge, the burst terminate command, TBST, can interrupt the burst read operation and disable the data output. The READ to TBST interval is a minimum of one CLK. TBST is mainly used to interrupt FP bursts. The figures below show examples, of how the output data is terminated with TBST.
Read Interrupted by Burst Terminate (BL=4)
CLK
Command
READ
TBST
DQ
Q0
Q1
Q2
Q3
Command
READ
TBST
CL=3
DQ Q0 Q1 Q2
Command
READ
TBST
DQ
Q0
Command
READ
TBST
DQ
Q0
Q1
Q2
Q3
Command
READ
TBST
CL=2
DQ Q0 Q1 Q2
Command
READ
TBST
DQ
Q0
Command
READ
TBST
DQ
Q0
Q1
Q2
Q3
CL=1
Command
READ
TBST
DQ
Q0
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SDRAM (Rev. 0.3)
MITSUBISHI LSIs
Feb `97 Preliminary
M5M4V4S40CTP-12, -15
4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM [ Write Interrupted by Write ] A burst write operation can be interrupted by a new write to the same or opposite bank. Random column access is allowed. WRITE to WRITE interval is a minimum of one CLK. Write Interrupted by Write (BL=4)
CLK Command A0-7 A8 BA DQ
Write Write Yi 0 0 Dai0 Yj 0 0 Daj0 Daj1 Write Yk 0 1 Write Yl 0 0 Dal1 Dal2 Dal3
Dbk0 Dbk1 Dbk2 Dal0
[ Write Interrupted by Read ] A burst write operation can be interrupted by a read of the same or opposite bank. Random column access is allowed. WRITE to READ interval is a minimum of one CLK. The input data on DQ at the interrupting READ cycle is "don't care".
Write Interrupted by Read (BL=4, CL=3)
CLK Command A0-7 A8 BA DQMU DQML DQ
Dai0 Qaj0 Qaj1 Dak0 Dak1 Qbl0 Write READ Yi 0 0 Yj 0 0 Write Yk 0 0 READ Yl 0 1
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SDRAM (Rev. 0.3)
MITSUBISHI LSIs
Feb `97 Preliminary
M5M4V4S40CTP-12, -15
4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM [ Write Interrupted by Precharge ] A burst write operation can be interrupted by precharging (PRE) the same bank. Write recovery time (tWR) is required between the last input data and the next PRE. This may require DQMU/DQML control depending on the CLK frequency and tWR timing. See the example below. Write Interrupted by Precharge (BL=4)
CLK Command A0-7 A8 BA DQMU DQML DQ
Dai0 Dai1 Write tWR Yi 0 0 0 0 PRE tRP Xb Xb 0 ACT
This data should be masked to satisfy tWR requirement.
[ Write Interrupted by Burst Terminate ] A burst terminate command TBST can be used to terminate a burst write operation. In this case, the write recovery time is not required and the bank remains active (Please see the waveforms below). The WRITE to TERM minimum interval is one CLK. Write Interrupted by Burst Terminate (BL=4)
CLK Command A0-7 A8 BA DQMU DQML DQ
Dai0 Dai1 Dai2 Write Yi 0 0 TERM
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SDRAM (Rev. 0.3)
MITSUBISHI LSIs
Feb `97 Preliminary
M5M4V4S40CTP-12, -15
4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM AUTO REFRESH Auto-refresh is initiated with a REFA command (/CS= /RAS= /CAS= L, /WE= /CKE= H). The refresh address is generated internally. 1024 REFA cycles issued within 16.4ms will refresh the entire 4Mbit memory array. The auto-refresh is alternately performed on each bank (ping-pong). Before performing an auto-refresh, both banks must be in the idle state. Subsequent commands (except NOP or DESELECT) must not be asserted before tRC from the REFA command.
Auto-Refresh
CLK /CS NOP or DESLECT /RAS /CAS /WE CKE A0-8 BA minimum tRC
Auto Refresh on Bank 0
Auto Refresh on Bank 1
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SDRAM (Rev. 0.3)
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Feb `97 Preliminary
M5M4V4S40CTP-12, -15
4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM SELF REFRESH Self-refresh mode is entered by issuing a REFS command (/CS= /RAS= /CAS= L, /WE= H, CKE= L). Once initiated, the self-refresh is maintained as long as CKE is kept low. During the self-refresh mode, CKE is asynchronous and all other inputs including CLK are disabled and ignored. Disabling all inputs except CKE during self-refresh reduces power consumption. To exit the self-refresh, supply a stable CLK input, issue a DESEL or NOP command, and set CKE=H (REFSX). After tRC from REFSX both banks will be in the idle state new commands can be issued. Until the tRC time has expired, only DESELor NOP commands may be asserted after an REFSX command.
Self-Refresh
CLK
Stable CLK
/CS /RAS /CAS /WE CKE
NOP
new command
A0-8 BA
X 0
Self Refresh Entry
Self Refresh Exit
minimum tRC for recovery
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SDRAM (Rev. 0.3)
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M5M4V4S40CTP-12, -15
4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM CLK SUSPEND CKE controls the internal CLK in the following cycle. The figure below shows how CKE works. When CKE=L the next internal CLK is suspended. CLK suspend is used to power down, suspend the outputs, and to suspend the inputs. Except during the self-refresh mode, CKE is a synchronous input. CLK suspend can be performed either when the banks are active or idle; however, all commands issued in the following cycle are ignored.
ext.CLK
CKE
int.CLK
Power Down by CKE
CLK CKE Command
PRE NOP NOP Standby Power Down
NOP NOP NOP
NOP NOP
CKE Command
ACT NOP NOP
Active Power Down
NOP NOP NOP
NOP NOP
DQ Suspend by CKE
CLK CKE Command
Write READ
DQ
D0
D1
D2
D3
Q0
Q1
Q2
Q3
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SDRAM (Rev. 0.3)
MITSUBISHI LSIs
Feb `97 Preliminary
M5M4V4S40CTP-12, -15
4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM DQMU / DQML CONTROL DQMU and DQML are used to mask write data and disable read data. During write operations, DQMU and DQML mask the upper and lower bytes of input, respectively. The DQMU and DQML write mask is applied in the same clock cycle. During read operations, DQMU and DQML are used to "Hi-Z" the upper and lower bytes of output data, respectively. The DQMU and DQML to output "Hi-Z" latency is two, i.e., the output will be "Hi-Z" at the rising edge of second clock after DQM is applied.
DQMU/DQML Function
CLK Command DQML
Write READ
DQ(0-7)
D0
D2
D3
Q0
Q1
Q3
masked by DQML=High DQMU
disabled by DQML=High
DQ(8-15)
D0
D1
D3
Q0
Q2
Q3
masked by DQMU=High
disabled by DQMU=High
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SDRAM (Rev. 0.3)
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Feb `97 Preliminary
M5M4V4S40CTP-12, -15
4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM
ABSOLUTE MAXIMUM RATINGS
Symbol Vdd VddQ VI VO IO Pd Topr Tstg Parameter Supply Voltage Supply Voltage for Output Input Voltage Output Voltage Output Current Power Dissipation Operating Temperature Storage Temperature Ta = 25 C Conditions with respect to Vss with respect to VssQ with respect to Vss with respect to VssQ Ratings -0.5 ~ 4.6 -0.5 ~ 4.6 -0.5 ~ 5.5 -0.5 ~ 4.6 50 1000 0 ~ 70 -65 ~ 150 Unit V V V V mA mW C C
RECOMMENDED OPERATING CONDITIONS
(Ta=0 ~ 70C, unless otherwise noted)
Limits Symbol Vdd Vss VddQ VssQ VIH*1 VIL*2 Parameter Min. Supply Voltage Supply Voltage Supply Voltage for Output Supply Voltage for Output High-Level Input Voltage all inputs Low-Level Input Voltage all inputs 3.0 0 3.0 0 2.0 -0.3 Typ. 3.3 0 3.3 0 Max. 3.6 0 3.6 0 5.5 0.8 V V V V V V Unit
NOTES: 1. VIH (max) = 5.75V for pulse width less than 5ns. 2. VIL (min) = -1.0V for pulse width less than 5ns.
CAPACITANCE
(Ta=0 ~ 70C, Vdd = VddQ = 3.3 0.3v, Vss = VssQ = 0v, unless otherwise noted)
Symbol CI(A) CI(C) CI(K) CI/O Parameter Input Capacitance, address pin Input Capacitance, control pin Input Capacitance, CLK pin Input Capacitance, I/O pin VI=Vss f=1MHz Vi=25mVrms Test Condition Limits (max.) 5 5 5 7 Unit pF pF pF pF
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SDRAM (Rev. 0.3)
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Feb `97 Preliminary
M5M4V4S40CTP-12, -15
4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM
AVERAGE SUPPLY CURRENT from Vdd
(Ta=0 ~ 70C, Vdd = VddQ = 3.3 0.3v, Vss = VssQ = 0v, unless otherwise noted)
Limits(max) Symbol Parameter Test Conditions -12 Icc1s*1 operating current, single bank tRC=min, tCLK=min, BL=1, CL=3 Icc1d*1 Icc2h Icc2l Icc3 Icc4*1 Icc5 Icc6 operating current, dual bank standby current, CKE=H standby current, CKE=L active standby current burst current auto-refresh current self-refresh current tRC=min, tCLK=min, BL=1, CL=3 both banks idle, tCLK=min, CKE=H both banks idle, tCLK=min, CKE=L both banks active, tCLK=min, CKE=H tCLK=min, BL=4, CL=3, 1 bank idle tRC=min, tCLK=min CKE <0.2v 90 130 18 2 35 120 60 1 -15 75 110 16 2 30 100 50 1 mA mA mA mA mA mA mA mA Unit
NOTES: 1. Icc (max) is specified at the output open condition.
AC OPERATING CONDITIONS AND CHARACTERISTICS
(Ta=0 ~ 70C, Vdd = VddQ = 3.3 0.3v, Vss = VssQ = 0v, unless otherwise noted)
Limits Symbol Parameter Test Conditions Min. VOH (DC) High-Level Output Voltage (DC) VOL (DC) IOZ Low-Level Output Voltage (DC) Off-state Output Current Input Current IOH=-2mA IOL= 2mA Q floating VO=0 ~ VddQ VIH = 0 ~ VddQ+0.3V -10 -10 2.4 0.4 10 10 Max. V V A A Unit
II
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SDRAM (Rev. 0.3)
MITSUBISHI LSIs
Feb `97 Preliminary
M5M4V4S40CTP-12, -15
4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM
AC TIMING REQUIREMENTS
(Ta=0 ~ 70C, Vdd = VddQ = 3.3 0.3v, Vss = VssQ = 0v, unless otherwise noted) Input Pulse Levels : 0.8V to 2.0V Input Timing Measurement Level : 1.4V
Limits Symbol Parameter Min. CL=1 tCLK CLK cycle time CL=2 CL=3 tCH tCL tT tIS tIH tRC tRCD tRAS tRP tWR tRRD tRSC tPDE tREF CLK High pulse width CLK Low pulse width Transition time of CLK Input Setup time (all inputs) Input Hold time (all inputs) Row Cycle time Row to Column Delay Row Active time Row Precharge time Write Recovery time Act to Act Delay time Mode Register Set Cycle time Power Down Exit time Refresh Interval time 30 15 12 4 4 1 3 1 100 30 70 30 12 24 24 12 16.4 10000 10 -12 Max. Min. 30 15 15 4 4 1 3 1.5 120 30 75 40 15 30 30 15 16.4 10000 10 -15 Max. ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms Unit
CLK
1.4V
Signal
1.4V
Any AC timing is referenced to the input signal passing through 1.4V.
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SDRAM (Rev. 0.3)
MITSUBISHI LSIs
Feb `97 Preliminary
M5M4V4S40CTP-12, -15
4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM
SWITCHING CHARACTERISTICS
(Ta=0 ~ 70C, Vdd = VddQ = 3.3 0.3v, Vss = VssQ = 0v, unless otherwise noted)
Limits Symbol Parameter Min. CL=1 tAC Access time from CLK CL=2 CL=3 tCAC tRAC tOH Column Access Time Row Access Time Output Hold time from CLK Delay time, output low impedance from CLK Delay time, output high impedance from CLK 3 -12 Max. 27 9.5 8 24.5 54.5 3 Min. -15 Max. 30 12 9 30 60 ns ns ns ns ns ns Unit
tOLZ
0
0
ns
tOHZ
3
8
3
10
ns
Output Load Condition
VTT=1.4V CLK 1.4V
50 ohm
VREF =1.4V
DQ
1.4V
VOUT 50pF Output Timing Measurement Reference Point
CLK
1.4V
DQ
tAC tOH
tOHZ
1.4V
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SDRAM (Rev. 0.3)
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Feb `97 Preliminary
M5M4V4S40CTP-12, -15
4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM WRITE CYCLE (single bank) BL=4
CLK
tRC
/CS
tRAS tRP
/RAS
tRCD
/CAS
/WE
CKE DQMU DQML A0-7
X Y X
A8
X
X
BA
tWR D D D D
DQ
ACT
WRITE
PRE
ACT
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SDRAM (Rev. 0.3)
MITSUBISHI LSIs
Feb `97 Preliminary
M5M4V4S40CTP-12, -15
BL=4
4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM WRITE CYCLE (dual bank)
CLK
tRC
/CS
tRAS tRRD tRAS tRP
/RAS
tRCD tRCD
/CAS
/WE
CKE DQMU DQML A0-7
Xa Y Xb Y
A8
Xa
Xb
BA
tWR tWR Db Db Db Da Da Da Da Db
DQ
ACTa
WRITEa ACTb
WRITEb PREa
PREb
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SDRAM (Rev. 0.3)
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M5M4V4S40CTP-12, -15
4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM READ CYCLE (single bank) BL=4, CL=3
CLK
tRC
/CS
tRAS tRP
/RAS
tRCD
/CAS
/WE
CKE DQMU DQML A0-7
X Y X
A8
X
X
BA
Q Q Q Q
DQ
tRAC ACT READ
tCAC
PRE
ACT
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SDRAM (Rev. 0.3)
MITSUBISHI LSIs
Feb `97 Preliminary
M5M4V4S40CTP-12, -15
4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM READ CYCLE (dual bank) BL=4, CL=3
CLK
tRC
/CS
tRRD
tRAS tRAS
tRP
/RAS
tRCD tRCD
/CAS
/WE
CKE DQMU DQML A0-7
Xa Y Xb Y Xa
A8
Xa
Xb
Xa
BA
Qa tCAC tRAC ACTa READa ACTb tRAC READb PREa PREb ACTa Qa Qa Qa Qb Qb Qb Qb
DQ
tCAC
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SDRAM (Rev. 0.3)
MITSUBISHI LSIs
Feb `97 Preliminary
M5M4V4S40CTP-12, -15
4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM WRITE to READ (single bank) BL=4, CL=3
CLK
/CS
tRAS
/RAS
tRCD
/CAS
/WE
CKE DQMU DQML A0-7
X Y Y
A8
X
BA
D D D D tCAC ACT WRITE READ PRE Q Q Q Q
DQ
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SDRAM (Rev. 0.3)
MITSUBISHI LSIs
Feb `97 Preliminary
M5M4V4S40CTP-12, -15
4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM
WRITE to READ (dual bank)
BL=4, CL=3
CLK
tRC
/CS
tRRD
tRAS tRAS
tRP
/RAS
tRCD tRCD
/CAS
/WE
CKE DQMU DQML A0-7
Xa Y Xb Y Xa
A8
Xa
Xb
Xa
BA
tWR Da Da Da Da tCAC ACTa WRITEa ACTb READb PREa PREb ACTa Qb Qb Qb Qb
DQ
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SDRAM (Rev. 0.3)
MITSUBISHI LSIs
Feb `97 Preliminary
M5M4V4S40CTP-12, -15
BL=4,CL=3
4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM DQM Byte control for WRITE to READ (single bank)
CLK
/CS
tRAS
/RAS
tRCD
/CAS
/WE
CKE
DQML
DQMU
A0-7
X
Y
Y
A8
X
BA DQ (0-7) DQ (8-15)
ACT D D D D D D tCAC WRITE READ PRE Q Q Q Q Q Q
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SDRAM (Rev. 0.3)
MITSUBISHI LSIs
Feb `97 Preliminary
M5M4V4S40CTP-12, -15
4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM READ to WRITE (single bank) BL=4, CL=3
CLK
/CS
tRAS
/RAS
tRCD
/CAS
/WE
CKE DQMU DQML A0-7
for output disable
X
Y
Y
A8
X
BA
tWR Q tCAC tRAC ACT READ WRITE PRE Q D D D D
DQ
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SDRAM (Rev. 0.3)
MITSUBISHI LSIs
Feb `97 Preliminary
M5M4V4S40CTP-12, -15
4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM READ to WRITE (dual bank) BL=4, CL=3
CLK
tRC
/CS
tRAS tRRD tRAS tRP
/RAS
tRCD tRCD
/CAS
/WE
CKE
for output disable
DQMU DQML A0-7
Xa Y Xb Y Xa
A8
Xa
Xb
Xa
BA
tWR Qa tCAC tRAC READa ACTb Qa Db Db Db Db
DQ
ACTa
PREa
WRITEb
ACTa
PREb
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SDRAM (Rev. 0.3)
MITSUBISHI LSIs
Feb `97 Preliminary
M5M4V4S40CTP-12, -15
BL=4
4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM WRITE with AUTO-PRECHARGE (WRITEA)
CLK
tRC
/CS
tWR + tRP
/RAS
tRCD
/CAS
/WE
CKE DQMU DQML A0-7
X Y X
A8
X
X
BA
D D D D
DQ
ACT
WRITEA internal precharge starts this timing depends on BL
ACT
Note: WRITEA should not be used for Full Page (FP) burst operations.
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SDRAM (Rev. 0.3)
MITSUBISHI LSIs
Feb `97 Preliminary
M5M4V4S40CTP-12, -15
BL=4, CL=3
4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM READ with AUTO-PRECHARGE (READA)
CLK
tRC
/CS
tRP
/RAS
tRCD
/CAS
/WE
CKE DQMU DQML A0-7
X
Y
X
A8
X
X
BA
Q tCAC tRAC ACT READA internal precharge starts this timing depends on BL ACT Q Q Q
DQ
Note: READA should not be used for Full Page (FP) burst operations. MITSUBISHI ELECTRIC
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SDRAM (Rev. 0.3)
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M5M4V4S40CTP-12, -15
4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM AUTO-REFRESH
CLK
tRC
/CS
tRP
/RAS
/CAS
/WE
CKE DQMU DQML A0-7
A8
BA
DQ
PREA REFA REFA
if any bank is active, it must be precharged
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SDRAM (Rev. 0.3)
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M5M4V4S40CTP-12, -15
4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM SELF-REFRESH ENTRY
CLK
/CS
tRP
/RAS
/CAS
/WE
CKE DQMU DQML A0-7
A8
BA
DQ
PREA REFS
if any bank is active, it must be precharged
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SDRAM (Rev. 0.3)
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M5M4V4S40CTP-12, -15
4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM SELF-REFRESH EXIT
CLK
/CS
NOP or DESEL
/RAS
/CAS
/WE
tRC
CKE DQMU DQML A0-7
X
A8
X
BA
DQ
ACT internal CLK re-start
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SDRAM (Rev. 0.3)
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M5M4V4S40CTP-12, -15
4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM MODE REGISTER SET BL=4, CL=3
CLK
/CS
tRP tRSC tRCD
/RAS
/CAS
/WE
CKE DQMU DQML A0-7
mode X
Y
A8
X
BA
Q tCAC tRAC Q Q
DQ
if any bank is active, it must be precharged
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